CYW43362
Figure 13. gSPI Signal Timing Without Status
Write
cs
sclk
mosi
CC3311 CC3300
CC11 CC00 DD3311 DD3300
DD11 DD00
Command 32 bits Write Data 16*n bits
Write-Read
cs
sclk
mosi
miso
CC3311 CC3300
CC00
CC00
DD3311 DD3300
DD00
DD11
Response
Delay
Command
32 bits
Read Data 16*n bits
cs
Read
sclk
mosi
miso
CC3311 CC3300
DD3311 DD3300
DD00
Command
32 bits
Response
Delay
Read Data
16*n bits
Document No. 002-14779 Rev. *G
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