PRELIMINARY
CYW43340
18.2 HSIC Interface Specifications
Table 45. HSIC Timing Parameters
Parameter
HSIC signaling voltage
I/O voltage input low
I/O Voltage input high
I/O voltage output low
I/O voltage output high
I/O pad drive strength
Symbol
Minimum
1.1
Typical
Maximum
1.3
Unit
Comments
VDD
VIL
1.2
–
V
V
V
V
V
Ω
–
–
–
–
–
–0.3
0.35 × VDD
VDD + 0.3
0.25 × VDD
–
VIH
VOL
VOH
OD
0.65 × VDD
–
–
–
0.75 × VDD
40
–
–
60
Controlled output
impedance driver
I/O weak keepers
IL
20
100
3
–
70
–
μA
kΩ
pF
Ω
–
–
–
–
–
–
I/O input impedance
Total capacitive loada
ZI
CL
–
–
14
55
10
15
Characteristic trace impedance TI
Circuit board trace length TL
45
–
50
–
cm
ps
Circuit board trace propagation TS
skewb
–
–
STROBE frequencyc
FSTROBE
239.988
240
1.0
240.012
1.2
MHz
V/ns
± 500 ppm
Slew rate (rise and fall) STROBE Tslew
and DATAC
0.60 × VDD
Averaged from
30% ~ 70% points
Receiver data setup time (with
respect to STROBE)c
Ts
300
300
–
–
–
–
ps
ps
Measured at the 50%
point
Receiver data hold time (with
respect to STROBE)c
Tb
Measured at the 50%
point
a.Total Capacitive Load (CL), includes device Input/Output capacitance, and capacitance of a 50Ω PCB trace with a length of 10 cm.
b.Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be matched between STROBE and DATA to ensure
that the signal timing is within specification limits at the receiver.
c.Jitter and duty cycle are not separately specified parameters, they are incorporated into the values in the table above.
18.3 JTAG Timing
Table 46. JTAG Timing Characteristics
Output
Output
Minimum
Signal Name
Period
125 ns
Setup
Hold
Maximum
TCK
TDI
–
–
–
–
–
–
–
–
20 ns
20 ns
–
0 ns
0 ns
–
TMS
TDO
–
–
–
100 ns
–
0 ns
–
JTAG_TRST
250 ns
–
–
Document Number: 002-14943 Rev. *L
Page 86 of 96
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