PRELIMINARY
CYW43340
Figure 34. WLAN = OFF, Bluetooth = OFF
32.678 kHz Sleep Clock
VBAT*
VDDIO
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first
or be held high before VBAT is high.
Figure 35. WLAN = ON, Bluetooth = OFF
32.678 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds.
2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first
or be held high before VBAT is high .
Document Number: 002-14943 Rev. *L
Page 88 of 96
CYPRESS [ CYPRESS ]
