BCM4330 Preliminary Data Sheet
SDIO/gSPI Timing
gSPI Signal Timing
The gSPI host and device always use the rising edge of clock to sample data.
T1
T4
T5
T2
T3
SPI_CLK
SPI_DIN
T6
T7
T8
T9
SPI_DOUT
(falling edge)
Figure 46: gSPI Timing
Table 49: gSPI Timing Parameters
Parameter
Symbol Minimum
Maximum
Units Note
ns = 48 MHz
max
Clock period
T1
20.8
–
F
Clock high/low
T2/T3
(0.45 × T1) – (0.55 × T1) – ns
–
T4
–
T4
2.5
–
Clock rise/falltime T4/T5
Input setup time T6
ns
ns
–
5.0
Setup time, SIMO valid to SPI_CLK active
edge
Input hold time T7
Output setup time T8
5.0
5.0
5.0
–
–
–
ns
ns
ns
Hold time, SPI_CLK active edge to SIMO
invalid
Setup time, SOMI valid before SPI_CLK
rising
Hold time, SPI_CLK active edge to SOMI
invalid
CSX fall to 1st rising edge
Output hold time T9
a
CSX to clock
Clock to CSX
–
–
7.86
–
–
–
ns
ns
a
Last falling edge to CSX high
a. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (i.e., overall words for
multiple word transaction)
®
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BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 155
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