BCM4330 Preliminary Data Sheet
SDIO/gSPI Timing
Table 47: SDIO Bus Timinga Parameters (Default Mode)
Symbol Minimum Typical
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Parameter
Maximum Unit
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
Clock high time
Clock rise time
fPP
0
0
10
10
–
–
–
–
–
–
–
25
400
–
–
10
10
MHz
kHz
ns
ns
ns
fOD
tWL
tWH
tTLH
tTHL
Clock low time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
Output delay time – Identification mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL 40pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
®
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BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 153
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