CYW20702
Table 26. PCM Interface Timing Specifications (Long Frame Synchronization, Slave Mode)
Reference Characteristics Minimum
PCM bit clock frequency. 128
Maximum
2048
Unit
1
2
3
4
kHz
ns
PCM bit clock HIGH time.
PCM bit clock LOW time.
209
209
50
–
–
–
ns
Setup time for PCM_SYNC before falling edge of PCM_BCLK
during first bit time.
ns
5
6
Hold time for PCM_SYNC after falling edge of PCM_BCLK during 10
second bit period. (PCM_SYNC may go low any time from second
bit period to last bit period).
–
ns
ns
Delay from rising edge of PCM_BCLK or PCM_SYNC
(whichever is later) to data valid for first bit on PCM_OUT.
–
50
7
8
9
Hold time of PCM_OUT after PCM_BCLK falling edge.
Setup time for PCM_IN before PCM_BCLK falling edge.
Hold time for PCM_IN after PCM_BCLK falling edge.
–
175
–
ns
ns
ns
ns
50
10
–
–
10
Delay from falling edge of PCM_BCLK or PCM_SYNC
(whichever is later) during last bit in slot to PCM_OUT becoming
high impedance.
100
Figure 17. PCM Interface Timing (Long Frame Synchronization, Slave Mode)
2
1
PCM_BCLK
PCM_SYNC
3
4
5
7
6
10
HIGH
IMPEDENCE
Bit 0
Bit 1
Bit 15
PCM_OUT
PCM_IN
8
9
Bit 0
Bit 1
Bit 15
Document Number: 002-14773 Rev. *L
Page 45 of 55
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