CYW20702
9.2.6 SPI Timing
The SPI interface can be clocked up to 12 MHz.
Table 28 and Figure 20 show the timing requirements when operating in SPI Mode 0 and 2.
Table 28. SPI Mode 0 and 2
Reference
Characteristics
Minimum
Maximum
Unit
1
2
Time from slave assert SPI_INT to master assert SPI_CSN
(DirectRead)
0
0
∞
ns
Time from master assert SPI_CSN to slave assert SPI_INT
(DirectWrite)
∞
ns
3
4
5
6
7
8
Time from master assert SPI_CSN to first clock edge
Setup time for MOSI data lines
20
8
∞
ns
ns
ns
ns
ns
ns
½ SCK
½ SCK
100
Hold time for MOSI data lines
8
Time from last sample on MOSI/MISO to slave deassert SPI_INT 0
Time from slave deassert SPI_INT to master deassert SPI_CSN 0
∞
∞
Idle time between subsequent SPI transactions
1 SCK
Figure 19. SPI Timing, Mode 0 and 2
8
SPI_CSN
SPI_INT
(DirectWrite)
2
SPI_INT
(DirectRead)
1
3
SPI_CLK
(Mode 0)
SPI_CLK
(Mode 2)
4
5
‐
First Bit
‐
Second Bit
Second Bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
First Bit
Not Driven
Not Driven
Document Number: 002-14773 Rev. *L
Page 47 of 55
CYPRESS [ CYPRESS ]
