CYW20702
Table 24. PCM Interface Timing Specifications (Short Frame Synchronization, Slave Mode)
Reference Characteristics Minimum
PCM bit clock frequency 128
Maximum
2048
Unit
1
2
3
4
5
6
7
8
9
kHz
ns
ns
ns
ns
ns
ns
ns
ns
PCM bit clock HIGH time
209
209
50
10
–
–
PCM bit clock LOW time
–
Setup time for PCM_SYNC before falling edge of PCM_BCLK
Hold time for PCM_SYNC after falling edge of PCM_BCLK
Hold time of PCM_OUT after PCM_BCLK falling edge
Setup time for PCM_IN before PCM_BCLK falling edge
Hold time for PCM_IN after PCM_BCLK falling edge
–
–
175
–
50
10
–
–
Delay from falling edge of PCM_BCLK during last bit period
to PCM_OUT becoming high impedance
100
Figure 15. PCM Interface Timing (Short Frame Synchronization, Slave Mode)
2
1
3
PCM_BCLK
4
5
PCM_SYNC
6
9
HIGH
IMPEDENCE
Bit 15 (Previous Frame)
Bit 0
Bit 15
PCM_OUT
PCM_IN
7
8
Bit 15 (Previous Frame)
Bit 0
Bit 15
Document Number: 002-14773 Rev. *L
Page 43 of 55
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