CYW20702
9.2.3 UART Timing
Table 22. UART Timing Specifications
Reference
Characteristics
Minimum
Maximum
Unit
1
Delay time, UART_CTS_N low to UART_TXD valid
–
24
Baudout
cycles
2
3
Setup time, UART_CTS_N high before midpoint of stop bit
Delay time, midpoint of stop bit to UART_RTS_N high
–
–
10
2
ns
Baudout
cycles
UART_CTS_N
2
1
UART_TXD
Midpoint of STOP
bit
Midpoint of STOP
bit
UART_RXD
3
UART_RTS_N
Figure 13. UART Timing
9.2.4 PCM Interface Timing
Table 23. PCM Interface Timing Specifications (Short Frame Synchronization, Master Mode)
Reference Characteristics Minimum
PCM bit clock frequency 128
Maximum
Unit
1
2
3
4
5
6
7
8
9
2048
–
kHz
ns
ns
ns
ns
ns
ns
ns
ns
PCM bit clock HIGH time
128
209
–
PCM bit clock LOW time
–
Delay from PCM_BCLK rising edge to PCM_SYNC high
Delay from PCM_BCLK rising edge to PCM_SYNC low
Delay from PCM_BCLK rising edge to data valid on PCM_OUT
Setup time for PCM_IN before PCM_BCLK falling edge
Hold time for PCM_IN after PCM_BCLK falling edge
50
50
50
–
–
–
50
10
–
–
Delay from falling edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
50
Document Number: 002-14773 Rev. *L
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