CYW20702
Table 29 and Figure 20 show the timing requirements when operating in SPI Mode 0 and 2.
Table 29. SPI Mode 1 and 3
Reference
Characteristics
Minimum
Maximum
Unit
1
2
Time from slave assert SPI_INT to master assert
SPI_CSN (DirectRead)
0
0
∞
ns
Time from master assert SPI_CSN to slave assert
SPI_INT (DirectWrite)
∞
ns
3
4
5
6
Time from master assert SPI_CSN to first clock edge
Setup time for MOSI data lines
20
8
∞
ns
ns
ns
ns
½ SCK
½ SCK
100
Hold time for MOSI data lines
8
Time from last sample on MOSI/MISO to slave
deassert SPI_INT
0
7
8
Time from slave deassert SPI_INT to master
deassert SPI_CSN
0
∞
∞
ns
ns
Idle time between subsequent SPI transactions
1 SCK
Figure 20. SPI Timing, Mode 1 and 3
SPI_CSN
8
SPI_INT
(DirectWrite)
2
7
6
SPI_INT
(DirectRead)
1
SPI_CLK
3
(Mode 1)
SPI_CLK
(Mode 3)
4
5
‐
Invalid bit
Invalid bit
‐
First bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
Not Driven
Not Driven
First bit
Document Number: 002-14773 Rev. *L
Page 48 of 55
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