CYW20702
9.2 Timing and AC Characteristics
In this section, use the numbers listed in the reference column to interpret the timing diagrams.
9.2.1 Startup Timing
There are two basic startup scenarios. In one scenario, the chip startup and firmware boot is held off while the RST_N pin is asserted.
In the second scenario, the chip startup and firmware boot is directly triggered by the chip power-up. In this case, an internal power-
on reset (POR) is held for a few ms, after which the chip commences startup.
The global reset signal in the CYW20702 is a logical OR (actually a wired AND, since the signals are active low) of the RST_N input
and the internal POR signals. The last signal to be released determines the time at which the chip is released from reset. The POR
is typically asserted for 3 ms after VDDC crosses the 0.8V threshold, but it may be as soon as 1.5 ms after this event.
After the chip is released from reset, both startup scenarios follow the same sequence, as follows:
1. For the CYW20702A1KWFBG part: After approximately 120 μs, the CLK_REQ (GPIO_5) signal is asserted.
2. The chip remains in sleep state for a minimum of 4.2 ms.
3. If present, the crystal (or TCXO) and LPO clocks must be oscillating by the end of the 4.2 ms period.
If a TCXO clock is not in the system, a crystal is assumed to be present at the XIN and XOUT pins. If an LPO clock is not used, the
firmware will detect the absence of a clock at the LPO_IN lead and use the internal LPO clock instead.
The following two figures illustrate two startup timing scenarios.
Figure 10. Startup Timing from RST_N
trampmax = 200
μs
VDDIO, VBAT,REG_EN
VREG
VDDC > 0.8V
μs
t = 800
RST_N
t =64 to 171 μs
GPIO5 (CLK_REQ)
tmax = 4.2 ms
XTAL/TCXO
LPO
Document Number: 002-14773 Rev. *L
Page 39 of 55
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