Table C-6. T2CON Register - SFR C8h
Bit
Function
T2CON.0
CP/RL2 - Capture/reload flag. When CP/RL2 = 1, Timer 2
captures occur on high-to-low transitions of the T2EX pin, if
EXEN2 = 1. When CP/RL2 = 0, auto-reloads occur when
Timer 2 overflows or when high-to-low transitions occur on
the T2EX pin, if EXEN2 = 1. If either RCLK or TCLK is set
to 1, CP/RL2 will not function and Timer 2 will operate in
auto-reload mode following each overflow.
C.2.8.3 6-Bit Timer/Counter Mode with Capture
The Timer 2 capture mode (Figure C-4.) is the same as the 16-bit timer/counter mode, with the
addition of the capture registers and control signals.
The CP/RL2 bit in the T2CON SFR enables the capture feature. When CP/RL2 = 1, a high-to-
low transition on the T2EX pin when EXEN2 = 1 causes the Timer 2 value to be loaded into
the capture registers RCAP2L and RCAP2H.
T2M
Divide by 12
0
CLK24
C/T2
0
1
1
7
8
0
0
15
15
CLK
TL2
TH2
Divide by 4
T2 pin
RCAP2L
RCAP2H
TF2
TR2
7 8
EXEN2
CAPTURE
INT
EXF2
T2EX pin
Figure C-4. Timer 2 - Timer/Counter with Capture
EZ-USB TRM v1.9
Appendix C: 8051 Hardware Description
C - 11
CYPRESS [ CYPRESS ]
