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AN2131QC 参数 Datasheet PDF下载

AN2131QC图片预览
型号: AN2131QC
PDF下载: 下载PDF文件 查看货源
内容描述: 在EZ - USBTM集成电路 [The EZ-USBTM Integrated Circuit]
分类和应用:
文件页数/大小: 334 页 / 1468 K
品牌: CYPRESS [ CYPRESS ]
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Table B-6. PSW Register - SFR D0h  
Bit  
Function  
PSW.7  
CY - Carry flag. This is the unsigned carry bit. The CY flag is  
set when an arithmetic operation results in a carry from bit 7 to  
bit 8, and cleared otherwise. In other words, it acts as a virtual  
bit 8. The CY flag is cleared on multiplication and division.  
PSW.6  
AC - Auxiliary carry flag. Set to 1 when the last arithmetic  
operation resulted in a carry into (during addition) or borrow  
from (during subtraction) the high order nibble, otherwise  
cleared to 0 by all arithmetic operations.  
PSW.5  
PSW.4  
PSW.3  
F0 - User flag 0. Bit-addressable, general purpose flag for  
software control.  
RS1 - Register bank select bit 1. used with RS0 to select a  
register bank in internal RAM.  
RS0 - Register bank select bit 0, decoded as:  
RS1 RS0 Banks Selected  
0
0
1
1
0
1
0
1
Register bank 0, addresses 00h-07h  
Register bank 1, addresses 08h-0Fh  
Register bank 2, addresses 10h-17h  
Register bank 3, addresses 18h-1Fh  
PSW.2  
OV - Overflow flag. This is the signed carry bit. The OV flag  
is set when a positive sum exceeds 7fh, or a negative sum (in  
two’s compliment notation) exceeds 80h. On a multiply, if OV  
= 1, the result of the multiply is greater than FFh. On a divide,  
OV = 1 on a divide by 0.  
PSW.1  
PSW.0  
F1 - User flag 1. Bit-addressable, general purpose flag for  
software control.  
P - Parity flag. Set to 1 when the modulo-2 sum of the 8 bits in  
the accumulator is 1 (odd parity), cleared to 0 on even parity.  
B - 16  
Appendix B: 8051 Architectural Overview  
EZ-USB TRM v1.9  
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