IN07IRQ
Endpoint 0-7 IN Interrupt Request
7FA9
b7
b6
b5
b4
b3
b2
b1
b0
IN7IR
IN6IR
IN5IR
IN4IR
IN3IR
IN2IR
IN1IR
IN0IR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
OUT07IRQ
Endpoint 0-7 OUT Interrupt Requests
7FAA
b7
b6
b5
b4
b3
b2
b1
b0
OUT7IR
OUT6IR
OUT5IR
OUT4IR
OUT3IR
OUT2IR
OUT1IR
OUT0IR
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Figure 12-17. IN/OUT Interrupt Request (IRQ) Registers
These interrupt request (IRQ) registers indicate the pending interrupts for each bulk end-
point. An interrupt request (IR) bit becomes active when the BSY bit for an endpoint
makes a transition from one to zero (the endpoint becomes un-busy, giving access to the
8051). The IR bits function independently of the Interrupt Enable (IE) bits, so interrupt
requests are held whether or not the interrupts are enabled.
The 8051 clears an interrupt request bit by writing a “1” to it (see the following Note).
Note
Do not clear an IRQ bit by reading an IRQ register, ORing its contents with a bit mask,
and writing back the IRQ register. This will clear ALL pending interrupts. Instead, sim-
ply write the bit mask value (with the IRQ you want to clear) directly to the IRQ register.
Page 12-20
Chapter 12. EZ-USB Registers
EZ-USB TRM v1.9
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