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AN2131QC 参数 Datasheet PDF下载

AN2131QC图片预览
型号: AN2131QC
PDF下载: 下载PDF文件 查看货源
内容描述: 在EZ - USBTM集成电路 [The EZ-USBTM Integrated Circuit]
分类和应用:
文件页数/大小: 334 页 / 1468 K
品牌: CYPRESS [ CYPRESS ]
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Bit 2:  
SUTOKIR SETUP Token Interrupt Request  
The EZ-USB core sets this bit to “1” when it receives a SETUP token. Write a “1” to this  
bit to clear the interrupt request. See Chapter 7, "EZ-USB Endpoint Zero" for more infor-  
mation on the handling of SETUP tokens.  
Because this bit can change state while the 8051 is in reset, it may be active when the 8051  
comes out of reset, although it is reset to “0” by a power-on reset.  
Bit 1:  
SOFIR  
Start of frame Interrupt Request  
The EZ-USB core sets this bit to “1” when it receives a SOF packet. Write a “1” to this bit  
to clear the interrupt condition.  
Because this bit can change state while the 8051 is in reset, it may be active when the 8051  
comes out of reset, although it is reset to “0” by a power-on reset.  
Bit 0:  
SUDAVIR  
SETUP data available Interrupt Request  
The EZ-USB core sets this bit to “1” when it has transferred the eight data bytes from an  
endpoint zero SETUP packet into internal registers (at SETUPDAT). Write a “1” to this  
bit to clear the interrupt condition.  
Because this bit can change state while the 8051 is in reset, it may be active when the 8051  
comes out of reset, although it is reset to “0” by a power-on reset.  
Page 12-22  
Chapter 12. EZ-USB Registers  
EZ-USB TRM v1.9  
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