IN07EN
Endpoint 0-7 IN Interrupt Enables
7FAC
b7
b6
b5
b4
b3
b2
b1
b0
IN7IEN
IN6IEN
IN5IEN
IN4IEN
IN3IEN
IN2IEN
IN1IEN
IN0IEN
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
OUT07IEN
Endpoint 0-7 OUT Interrupt Enables
7FAD
b7
b6
b5
b4
b3
b2
b1
b0
OUT7IEN
OUT6IEN
OUT5IEN
OUT4IEN
OUT3IEN
OUT2IEN
OUT1IEN
OUT0IEN
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Figure 12-19. IN/OUT Interrupt Enable Registers
The Endpoint Interrupt Enable registers define which endpoints have active interrupts.
They do not affect the endpoint action, only the generation of an interrupt in response to
endpoint events.
When the IEN bit for an endpoint is “0,” the interrupt request bit for that endpoint is
ignored, but saved. When the IEN bit for an endpoint is “1,” any IRQ bit equal to “1” gen-
erates an 8051 INT2 request.
Note
The INT2 interrupt (EIE.0) and the 8051 global interrupt enable (EA) must be enabled
for the endpoint interrupts to propagate to the 8051. Once the INT2 interrupt is active, it
must be cleared by software.
EZ-USB TRM v1.9
Chapter 12. EZ-USB Registers
Page 12-23
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