12.8 230-Kbaud UART Operation - AN2122, AN2126
UART230
230-Kbaud UART Control
7F9F
b7
b6
b5
b4
b3
b2
b1
b0
-
-
-
-
-
-
UART1
UART0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Figure 12-10. 230-Kbaud UART Operation Register
Bit 1:
Bit 0:
UART1
UART0
Universal 115/230 Kbaud operation for UART1
Universal 115/230 Kbaud operation for UART0
These bits, when set to “1,” connect an internal 3.69-MHz clock to UART0 and/or
UART1. The UARTs divide this frequency by 16, giving a 230-KHz baud clock if the cor-
responding SMOD bit is set, or 115 baud clock if the corresponding SMOD bit is clear.
(NOTE: SMOD0 is bit 7 or SFR 0x87, SMOD1 is bit 7 or SFR 0xD8). When the UART0
or UART1 bit is clear, the normal UART clock sources are used.
12.9 Isochronous Control/Status Registers
ISOERR
Isochronous OUT EP Error
7FA0
b7
b6
b5
b4
b3
b2
b1
b0
ISO15ERR ISO14ERR ISO13ERR ISO12ERR ISO11ERR ISO10ERR ISO9ERR
ISO8ERR
R
x
R
x
R
x
R
x
R
x
R
x
R
x
R
x
Figure 12-11. Isochronous OUT Endpoint Error Register
The ISOERR bits are updated at every SOF. They indicate that a CRC error was received
on a data packet for the current frame. The ISOERR bit status refers to the USB data
received in the previous frame, and which is currently in the endpoint’s OUT FIFO. If the
ISOERR bit = 1, indicating a bad CRC check, the data is still available in the OUTnDATA
register.
Page 12-14
Chapter 12. EZ-USB Registers
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
