CY7C1351
Switching Waveforms (continued)
Burst Sequences
CLK
t
t
ALH
ALS
t
t
CL
t
CYC
CH
ADV/LD
ADDRESS
WE
t
t
AH
AS
RA1
WA2
RA3
t
t
WS
WH
t
t
WS
WH
BWS
CE
[3:0]
t
t
CES
CEH
t
t
t
CLZ
CHZ
t
DH
DOH
t
CLZ
Q3
Out
Q1
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
In
Data-
In/Out
Q1+1
Out
D2+1
In
Q3+1
Out
1a
Out
t
CDV
t
t
CDV
DS
Device
originally deselected
The combination of WE & BWS
defines a write cycle (see Write Cycle Description table).
[3:0]
CE is the combination of CE , CE , and CE . All chip enables need to be active in order to select
1
2
3
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS
input signals.
[3:0]
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
11
CYPRESS [ CYPRESS ]
