RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.3 Transmit Payload Mapper
The following configurations can cause the HDSL frame to become corrupted:
DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte #33.
TFIFO or CBank_1 is the source of data for HDSL payload byte #0.
The LSB of the DBank_1 pattern is equal to one (1).
or
DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte #33.
DBank_2 is the source of data for HDSL payload byte #0.
The LSB of the DBank_2 pattern is equal to one (1).
or
DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte #33.
DBank_3 is the source of data for HDSL payload byte #0.
The LSB of the DBank_3 pattern is equal to one (1).
0x0D—Transmit FIFO Reset (TFIFO_RST)
Writing any data value to TFIFO_RST empties the TFIFO, forces the HDSL transmitter to resample the
Transmit FIFO Water Level [TFIFO_WL; addr 0x05], and realigns the HDSL channel’s transmit 6 ms frame to
the PCM 6 ms frame. The MPU must write TFIFO_RST after modifying the TFIFO_WL value, the Transmit
Payload Map [TMAP; addr 0x08], or the PCM Routing Table [ROUTE_TBL; addr 0xED] each time PCM
MultiFrame Sync (TMSYNC) experiences a change of frame alignment and whenever the TFIFO reports an
overflow, underflow, or slip error. The RS8953B asserts TFIFO_RST automatically whenever a transmit STUFF
error is detected.
NOTE:
Each write to TFIFO_RST may cause TFIFO errors in the next three subsequent
HDSL frames. Therefore, the MPU must ignore up to three TFIFO errors reported in
the respective channel for the next 3 HDSL frames after writing the TFIFO_RST
command.
0x0E—Scrambler Reset (SCR_RST)
Writing any data value to SCR_RST sets the 23 stages of the scrambler LFSR to 0x000001. SCR_RST is used
during the Conexant production test to verify scrambler operation, and is not required during normal operation.
N8953BDSB
Conexant
4-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
