4.0 Registers
RS8953B/8953SPB
4.4 HDSL Receive
HDSL Channel Unit
4.4 HDSL Receive
HDSL Channel 1
(CH1)
HDSL Channel 2
(CH2)
HDSL Channel 3
(CH3)
Base Address
0x60
0x80
0xA0
Table 4-3. HDSL Receive Write Registers
CH1
CH2
CH3
Register Label
Bits
Name/Description
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x70
0x71
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x70
0x71
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xA0
0xA1
RCMD_1
RCMD_2
RFIFO_RST
SYNC_RST
RMAP_1
RMAP_2
RMAP_3
RMAP_4
RMAP_5
RMAP_6
ERR_RST
RSIG_LOC
8
8
–
–
6
6
6
6
6
6
–
4
Configuration
Configuration
Receive FIFO Reset
Receive Framer Reset
Payload Map
Payload Map
Payload Map
Payload Map
Payload Map
Payload Map
Error Count Reset
Receive Signaling Location
Three identical groups of write-only registers configure the HDSL receivers, and control the mapping of HDSL
payload bytes into the receiver elastic stores (RFIFO). Configuration registers define each HDSL receive
framer’s criteria for loss and recovery of frame alignment by selecting the number of detected SYNC word
errors used to declare loss of sync or needed to acquire sync. Refer to the Framer Synchronization State
Diagram, Figure 3-23. Frame alignment criteria are programmable to meet different standard application
requirements.
4-18
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
