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RS8953BEPJ 参数 Datasheet PDF下载

RS8953BEPJ图片预览
型号: RS8953BEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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4.0 Registers  
RS8953B/8953SPB  
4.4 HDSL Receive  
HDSL Channel Unit  
0x61—Receive Command Register 2 (RCMD_2)  
7
6
5
4
3
2
1
0
RX_ERR_EN  
PH_LOOP  
DSCR_EN  
DSCR_TAP  
THRESH_CORR[3:0}  
THRESH_CORR[3:0] SYNC Threshold Correlation—Upon the receive framers entry to a Sync Errored state, the  
number of SYNC word locations searched is determined by the result of the previous states’  
threshold correlation. During an In Sync state, the framer searches the two most probable  
SYNC word locations at 6 ms ± 1 quat, corresponding to 0 or 4 STUFF bits. One of the two  
locations searched must correctly match the entire 14-bit SYNC word or the framer enters a  
Sync Errored state. The highest number of matching bits found among the search locations is  
compared to the selected THRESH_CORR value to determine whether the framer should  
expand the number of search locations. If the highest number of matching bits meets or  
exceeds the threshold, but was not a complete match, the framer progresses to the next Sync  
Errored state and continues to each of the two most probable locations. Otherwise, the framer  
progresses to the next Sync Errored state, increments the number of locations to be searched,  
and examines quats on either side of the prior search locations. For example, if the location  
with the highest number of matching bits is below the threshold during In Sync, then the  
framer enters the first Sync Errored state and searches from the prior location at 6 ms ± 2  
quats, and at exactly 6 ms. The effect of threshold correlation on the number of search  
locations is depicted in Figure 3-24.  
THRESH_CORR  
SYNC Threshold Correlation  
10 or more out of 14 bits  
11 or more out of 14 bits  
12 or more out of 14 bits  
13 or more out of 14 bits  
14 out of 14 bits  
1010  
1011  
1100  
1101  
1110  
DSCR_TAP  
DSCR_EN  
Descrambler Tap—Selects which delay stage, 5th or 18th, to tap for feedback in the  
descrambler. The systems terminal type dictates which tap should be selected.  
0 = HTU-C or LTU terminal type, descrambler selects tap 18  
1 = HTU-R or NTU terminal type, descrambler selects tap 5  
Descrambler Enable—When enabled, all receive HDSL channel data, except SYNC and  
STUFF bits, are descrambled per the DSCR_TAP setting. Otherwise the data passes through  
the descrambler unchanged. DSCR_EN also determines whether RSER and RAUXn data are  
descrambled.  
0 = Descrambler bypassed  
1 = Descrambler enabled  
PH_LOOP  
Loopback to PCM on HDSL Side—Transmit HDSL data (TDATn) is connected back towards  
the PCM interface to accomplish a loopback of the PCM channel on the HDSL side. Receive  
HDSL data (RDATn) is ignored, but HDSL transmit continues without interruption.  
PH_LOOP requires the descrambler and scrambler to use the same tap, as opposed to their  
normal opposing tap selection.  
0 = Normal receive  
1 = RDATn supplied by TDATn  
4-20  
Conexant  
N8953BDSB