RS8953B/8953SPB
3.0 Circuit Descriptions
3.3 Clock Recovery DPLL
HDSL Channel Unit
3.3 Clock Recovery DPLL
The Digital Phase Locked Loop (DPLL) shown in Figure 3-14 synthesizes the
PCM Receive Clock (RCLK) from a 60–80 MHz High Frequency Clock
(HFCLK). HFCLK is developed by analog PLL multiplication of the MCLK
input frequency, or HFCLK is applied directly to the MCLK input (see
PLL_MUL and PLL_DIS in CMD_1; addr 0xE5). The analog PLL requires
external loop filter components and connections as shown in Figure 6-1. HFCLK
must be in the range of 60–80 MHz, but requires no specific frequency or phase
relationship to PCM or HDSL clocks. Open or closed loop operation is selected
by DPLL_NCO [CMD_5; addr E9].
Figure 3-14. DPLL Block Diagram
PLL
NCO
~ 15-20 MHz
SCLK
RCLK
÷ 4
x PLL_MUL
MCLK
HFCLK ~ 60-80 MHz
DPLL_FACTOR
÷ N-1
÷ N
÷ N+1
~ 12 MHz
GCLK
÷ PLL_DIV
PLL_DIS
÷ 2
Phase Detector
DPLL Filter
÷ N
÷ N+1
÷ N+2
DPLL_GAIN
CNT
Start
Stop
RST
CH1 RSYNC
CH2 RSYNC
CH3 RSYNC
HDSL 6ms
PCM 6ms
SUM
MASTER_SEL
-1
Z
DPLL_RST
DPLL_NCO
-1
Z
OVF
INIT
DPLL_RESID
÷ MF_CNT
÷ MF_LEN
÷ FRAME_LEN
N8953BDSB
Conexant
3-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
