3.0 Circuit Descriptions
RS8953B/8953SPB
3.2 PCM Channel
HDSL Channel Unit
3.2.2.4 RFIFO Water
Level
The RFIFO Water Level [RFIFO_WL; addr 0xCD] determines the PCM and
HDSL receiver’s phase error tolerance and receive throughput data delay by
establishing a fixed phase offset between the master HDSL channel’s receive 6 ms
frame and the PCM 6 ms sync, as shown in Figure 3-13. RFIFO_WL selects the
number of RCLK bit delays from HDSL to PCM 6 ms frames and controls the
amount of time available for the HDSL receiver to map data into the RFIFO
before the PCM receiver begins extracting data from the RFIFO. Because all or
part of an HDSL payload block can be mapped into a PCM frame, the system
must consider Receive Payload Map [RMAP; addr 0x64], Combination Table
[COMBINE_TBL; addr 0xEE] and other data path delays when programming
RFIFO_WL values.
Sufficient phase offset must be established to allow time for HOH, SYNC, and
STUFF bit extraction (20 HDSL bits), to load one payload byte (8 HDSL bits), to
unload one PCM timeslot (8 PCM bits), to account for differential transmission
delay (up to 65 µs) and PCM reconstruction (up to 96 PCM bits in T1 mode), and
time to tolerate clock variance (1 to 8 PCM bits).
Conversely, to avoid RFIFO overflow, phase offset must be limited so the
amount of data residing in the RFIFO never exceeds the number of PCM bits
mapped during one PCM frame, the maximum RFIFO depth (185 bits), or the
total HDSL payload block length [HFRAME_LEN; addr 0xCA].
The actual phase offset between HDSL and PCM 6 ms frames varies over time
as a result of STUFF bit extraction, clock variance, and differential phase delays.
Therefore, RFIFO_WL is only used to establish the initial phase offset between
HDSL and PCM receive frames when the MPU issues the Reset Receiver
command [RX_RST; addr 0xF1].
Figure 3-13. RFIFO Water Level Timing
Differential
Delay
16-bit SYNC + HOH
Z1
byte1 to RFIFO1
byte2
RDAT1
RDAT2
RDAT3
16-bit SYNC + HOH
Z
byte1 to RFIFO2
byte2
16-bit SYNC + HOH
Z
byte1 to RFIFO3
byte2
RFIFO_WL = PCM Bit Delay
PCM 6ms
Internal
0
1 2 3 4
RSER
RSER Bit 0, Frame 0
NOTE(S): CH1 selected as Master HDSL channel.
3-14
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
