3.0 Circuit Descriptions
RS8953B/8953SPB
3.3 Clock Recovery DPLL
HDSL Channel Unit
In closed loop operation, the Numerical Controlled Oscillator (NCO)
synthesizes the nominal RCLK frequency according to the programmed HFCLK
integer scale factor [DPLL_FACTOR; addr 0xD7] and the fractional scale factor
[DPLL_RESID; addr 0xD5]. The NCO locks the RCLK frequency to the HDSL
reference by varying the RCLK phase based on the filtered phase error from the
DPLL filter and the DPLL phase detector. Phase error is the phase difference
measured from the receive PCM 6 ms sync to the master HDSL channel’s 6 ms
frame. Phase error is quantized in units of GCLK, where GCLK is set to
approximately 12 MHz the from division of HFCLK by the programmed value of
PLL_DIV [CMD_1; addr 0xE5]. The phase detector measures and reports the
Phase Error [PHS_ERR; addr 0x38] coincident with the master HDSL channel’s
receive 6 ms frame interrupt. The phase detector automatically reinitializes, if
phase error exceeds ± 511 GCLK cycles according to the initialization mode
selected by PHD_MODE [CMD_7; addr 0xF4]. The DPLL filter is a Type II
digital filter in which the gain [DPLL_GAIN; addr 0xD8] determines the closed
loop DPLL filter bandwidth.
During open loop operation, the NCO synthesizes the RCLK frequency
according to the programmed HFCLK integer and fractional scale factors, but
ignores phase detector error outputs. In this case, RCLK frequency accuracy is
dependent on HFCLK accuracy (± 20 ppm) and programmed scale factor
accuracy (~ 2 Hz). Open loop operation is useful during remote HTU applications
to provide a stable RCLK output frequency while HDSL channels are performing
startup activities.
3-16
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
