RS8953B/8953SPB
3.0 Circuit Descriptions
HDSL Channel Unit
3.2 PCM Channel
Figure 3-10. PCM Receive Data Timing
HDSL 6ms
Master
RFIFO_WL = PCM Bit Delay
PCM 6ms
1 2 3 M
RFRAME_LOC[M] = RMSYNC Bit Delay
1 2 3 4 5 6 N
RMF_LOC[N] = RMSYNC Frame Delay
RMSYNC
FRAME_LEN[X] = PCM Frame Length
RSER
Bit
0
X
MF_LEN[Y] = PCM Multiframe Length
RSER
Frame
Frame 0
Frame Y
MF_CNT[Z] = PCM Mframes per 6 ms period
RSER
Mframe
Mframe 0
Mframe Z
NOTE(S): RMSYNC can mark any RSER bit position by programming RFAME_LOC and RMF_LOC.
N8953BDSB
Conexant
3-11