RS8953B/8953SPB
3.0 Circuit Descriptions
HDSL Channel Unit
3.2 PCM Channel
3.2.1.5 TFIFO Water
Levels
Each HDSL transmit channel aligns the start of its output frame with respect to
the PCM 6 ms sync according to the programmed TFIFO water level values
[TFIFO_WL; addr 0x05]. PCM 6 ms sync is created from MSYNC by the divisor
programmed in MF_CNT [addr 0xC7]. The HDSL 6 ms frame is created from
PCM 6 ms by adding the TFIFO_WL phase offset programmed for each channel,
as shown in Figure 3-8. In this manner, HDSL output frames are slaved to PCM
frame timing regardless of whether the system chooses to synchronize PCM data
to MSYNC.
The phase offset between PCM and HDSL 6 ms frames is programmed by
TFIFO_WL as the number of TCLK cycle delays from the start of PCM 6 ms
sync to the start of HDSL 6 ms frame. Thus, this phase offset determines the
amount of PCM data written to the TFIFO before the HDSL transmitter begins
extracting data from the TFIFO, which also defines each transmitter’s data
throughput delay and subsequently the differential delay with respect to other
HDSL channels. The actual phase offset varies over time as a result of stuff bit
insertion as well as PCM and HDSL clock jitter and wander. Therefore,
TFIFO_WL is only used to establish the initial phase offset between PCM and
HDSL frames when the MPU issues the TFIFO_RST [addr 0x0D] command, or
after a stuffing error.
Because all or part of the PCM frame can be routed to each HDSL channel,
the system must consider transmit routing table assignments and other data path
delays when programming TFIFO_WL values. Sufficient phase offset must be
established to allow time for the first programmed timeslot to be routed from the
PCM frame into the TFIFO, to absorb the phase offset created by HDSL
overhead, to stuff bit insertion and clock frequency variation, and to unload the
first timeslot from the TFIFO and map data into the HDSL payload byte.
Conversely, to avoid TFIFO overflow, phase offset must be limited so the amount
of data residing in the TFIFO does not exceed the number of PCM bits routed
during one PCM frame, the maximum TFIFO depth (186 bits), or the total HDSL
payload block length [HFRAME_LEN; addr 0xCA].
Figure 3-8. TFIFO Water Level Timing
Differential
Delay
MSYNC
PCM
0 1 2 3 4 5 6 7 8 910 X
Y
Z
(Bit)
CH1; TFIFO_WL[X]
HDSL
(CH1)
16-bit SYNC + HOH
Z
byte1 from TFIFO1
byte2
CH2; TFIFO_WL[Y]
HDSL
(CH2)
16-bit SYNC + HOH
Z
byte1 from TFIFO2
byte2
CH3; TFIFO_WL[Z]
HDSL
(CH3)
16-bit SYNC + HOH
Z byte1 from TFIFO3
NOTE(S):
1. PCM and HDSL shown synchronously mapped (PCM_FLOAT = 0).
2. Equal TFIFO_WL settings provide minimum differential delay.
N8953BDSB
Conexant
3-9
CONEXANT [ CONEXANT SYSTEMS, INC ]
