RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.10 Data Path Options
0xED—Transmit Routing Table (ROUTE_TBL)
MPU access to the transmit routing table’s single (ROUTE_TBL) register is enabled by first setting
ROUTE_EN [CMD_3; addr 0xE7] to reset the table pointer. The MPU can then write up to 64 table entries
sequentially to the ROUTE_TBL address. The RS8953B increments the internal table pointer after each write to
ROUTE_TBL.
Any writes beyond 64 will wrap around and overwrite the initial table entries. The first table entry written
corresponds to the first transmit PCM timeslot, which is the 8-bit period starting at MSYNC’s rising edge.
Subsequent table writes increment the table pointer towards successive PCM timeslots. Standard E1 requires 32
table writes, corresponding to 32 timeslots. Standard T1 requires 25 table writes, where the F-bit location is
treated as the 25th timeslot. An Nx64 transmit PCM channel may require up to 64 table writes, corresponding to
the 4.096 Mbit/s data rate. After the MPU writes the required number of table entries, the MPU writes zero to
ROUTE_EN to prevent further table access, and then write TFIFO_RST [addr 0x0D] on every HDSL channel
to realign the transmit elastic stores if the aggregate HDSL data rate is modified. Subsequent table changes can
rewrite only the necessary entries up to and including the last desired modification.
7
6
5
4
3
2
1
0
—
INSERT_EN
ROUTE[1:0] CH3
ROUTE[1:0] CH2
ROUTE[1:0] CH1
ROUTE[1:0]
Routing Code—Three identical routing codes are present in each table entry to select which
data source is routed to each one of three HDSL channel destinations (CH1–CH3). Route data
is available from three sources: PCM Transmit Serial data (TSER), PCM Insert Serial Data
(INSDAT), and PRBS generator data. In addition, TSER data is available from an 8-bit delay
buffer to allow routing codes to repeatedly (twice) use the same TSER byte as a data source.
PCM timeslot data can also be discarded by selecting no destination channels.
Note that INSDAT is available only from the 8-bit delay buffer, and cannot be repeated in
the same manner as TSER. INSDAT occupies delay buffer space and prevents routing of
previous TSER data during the timeslot following INSERT_EN. For example, if INSERT_EN
is active in the timeslot 1 table entry, then during timeslot 2, the delay buffer contains INSDAT,
and not the previous TSER. The PRBS generator is active only during timeslots that select
PRBS data which allows discontinuous timeslots to be tested with a single continuous PRBS
test pattern. Sequential timeslot routing is performed from inputs to destination channel(s)
without reordering of timeslots. Figure 4-1 illustrates the effect of ROUTE[1:0] and
INSERT_EN on TSER, INSDAT, and PRBS data routing.
ROUTE[1:0]
Source of Transmit HDSL Channel Data
Discard, do not route timeslot data
TSER
00
01
10
11
PRBS (or FILL_PATT, if PRBS_DIS = 1)
Previous TSER (or INSDAT) from delay buffer
Figure 4-1. Transmit Routing
TSER
INSDAT
PRBS
TFIFO1
TFIFO2
TFIFO3
Delay 8
INSERT_EN
ROUTE[1:0]
Ch. 1, 2, 3
N8953BDSB
Conexant
4-41
CONEXANT [ CONEXANT SYSTEMS, INC ]
