RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.9 DPLL Configuration
0xD8—DPLL Gain (DPLL_GAIN)
7
6
5
4
3
2
1
0
—
DC_GAIN[2:0]
DC_INTEG[3:0]
DPLL_GAIN[7:0]
DPLL Gain—Filtering is controlled by two DC parameters: DC_GAIN, which represents
proportional loop gain, and DC_INTEG, which represents the filter’s integration coefficient.
The DPLL closed loop bandwidth is programmed to be in the range of 0.2 Hz to 3 Hz. The
following approximations are used to calculate DC parameters for a desired DPLL bandwidth:
BW
N × 26.5
--------------------
DC_GAIN =
DC_INTEG =
× 217
(BW)2
215
---------------
-------
×
26.52
N
where: N = RCLK output frequency ÷ 64000
BW = DPLL closed loop bandwidth (in Hz)
Specific DC parameter values are programmed according to the following tables:
DC_GAIN[2:0]
000
RS8953B
25
26
001
010
011
100
101
110
111
27
28
29
210
211
212
DC_INTEG[3:0]
0000
RS8953B
2–4
2–3
0001
0010
0011
2–2
2–1
1
0100
0101
21
22
23
24
25
0110
0111
1000
1001
26
1010–1110
1111
0 (Type I)
N8953BDSB
Conexant
4-37
CONEXANT [ CONEXANT SYSTEMS, INC ]
