RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.10 Data Path Options
4.10 Data Path Options
Table 4-7. Data Path Options Write Registers
Address
Register Label
Bits
Name/Description
0xDC
0xDD
0xDE
0xEA
0xE4
0xED
0xEE
0xF2
DBANK_1
DBANK_2
8
8
8
8
4
7
6
4
Data Bank Pattern 1
Data Bank Pattern 2
Data Bank Pattern 3
DBANK_3
FILL_PATT
TSTUFF
Programmable Fill Pattern (Data Bank Pattern 4)
Transmit Stuff Bit Value
ROUTE_TBL
COMBINE_TBL
RSIG_TBL
Transmit Routing Table
Receive Combination Table
Receive Signaling Table
0xDC—Data Bank Pattern 1 (DBANK_1)
7
6
5
4
3
2
1
0
DBANK_1[7:0]
DBANK_1[7:0]
Data Bank Pattern 1—Holds an 8-bit programmable pattern that can be used to replace
transmit HDSL payload bytes and/or receive PCM timeslots according to the Transmit Payload
Map [TMAP; addr 0x08] and the Receive Combination Table [COMBINE_TBL; addr 0xEE]
selections. Both transmit and receive can simultaneously use the same DBANK contents.
DBANK_1[0] is the first bit inserted in the selected direction.
The following configuration can cause the HDSL frame to become corrupted:
DBank_1, DBank_2, or DBank_3 is the source of data for HDSL payload byte 33.
TFIFO or DBank_1 is the source of data for HDSL payload byte 0.
The LSB or the DBank_1 pattern is equal to one (1).
0xDD—Data Bank Pattern 2 (DBANK_2)
7
6
5
4
3
2
1
0
DBANK_2[7:0]
DBANK_2[7:0]
Data Bank Pattern 2—Provides another 8-bit pattern for insertion in transmit HDSL payload
bytes or receive PCM timeslots. See DBANK_1 above. Multiple DBANK registers may be
needed to fill transmit HDSL payload bytes reserved by ETSI standards for future
applications. For example, ETSI specifies R and Y bytes within a 2E1 payload block that are
currently set to all 1s.
N8953BDSB
Conexant
4-39
CONEXANT [ CONEXANT SYSTEMS, INC ]
