4.0 Registers
RS8953B/8953SPB
4.9 DPLL Configuration
HDSL Channel Unit
0xDB—DPLL Phase Detector Init (DPLL_PINI)
7
6
5
4
3
2
1
0
DPLL_PINI[7:0]
DPLL_PINI[7:0]
DPLL Phase Detector Init (optional for RS8953B)—Phase detector init mode [PHD_MODE
in CMD_7; addr 0xF4] selects whether DPLL_PINI is supplied by the MPU or is calculated
automatically. When MPU supplied, DPLL_PINI sets the initial point within the phase
comparator window that the phase detector returns to after detection of a DPLL error. The
RS8953B phase window is 1,024 GCLK cycles. For example, the RS8953B requires a
programmed value for DPLL_PINI which is typically set to init phase window at its center
point (i.e., 512 GCLK cycles) from the following formula:
512 × BCLK
4 × GCLK
------------------------------
DPLL_PINI = round
NOTE:
The loaded value is internally multiplied by 4 when used to initialize the phase
detector.
0xF6—Reset DPLL Phase Detector (DPLL_RST)
Writing any data value to DPLL_RST clears the phase detector error output, restarts the phase comparator
window, and clears pending DPLL error interrupts. The MPU is not required to write DPLL_RST, unless the
MPU has instructed the Phase Detector Init Mode [PHD_MODE in CMD_7; addr 0xF4] to disable automatic
initialization, or unless FAST_ACQ in CMD_7 is enabled and the system needs to reacquire the DPLL
frequency.
4-38
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
