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RS8953SPBEPJ 参数 Datasheet PDF下载

RS8953SPBEPJ图片预览
型号: RS8953SPBEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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RS8953B/8953SPB  
4.0 Registers  
HDSL Channel Unit  
4.11 Common Command  
0xE6—Command Register 2 (CMD_2)  
7
6
5
4
3
2
1
0
GCLK_SEL  
PCM_FLOAT  
HP_LOOP  
PP_LOOP  
RCLK_SEL[1:0]  
TCLK_SEL[1:0]  
TCLK_SEL  
PCM Transmit Clock Source—Selects which clock source and clock edge are used for PCM  
transmit inputs and outputs.  
00  
01  
1x  
TCLK (rising edge outputs, falling edge inputs)  
TCLK inverted (falling edge outputs, rising edge inputs)  
PCM receive clock source (see RCLK_SEL)  
RCLK_SEL  
PCM Receive Clock Source—Selects which clock source and which clock edge is used for  
PCM receive outputs. See also RCLK_INV [CMD_7; addr 0xF4].  
00  
01  
10  
11  
DPLL recovered clock (rising edge outputs)  
EXCLK pin (rising edge outputs)  
EXCLK pin inverted (falling edge outputs)  
PCM transmit clock source (see TCLK_SEL)  
NOTE:  
TCLK_SEL = 1x and RCLK_SEL = 11; both must not be set simultaneously.  
PP_LOOP  
Loopback Towards PCM on the PCM Side—The RSER and RMSYNC outputs are connected  
from TSER and TMSYNC inputs. Signals are switched directly at the I/O pins, without  
switching the PCM receive clock. The MPU must change RCLK_SEL to source RCLK from  
the TCLK input. HDSL transmit and receive channels operate normally, except the receive  
channel outputs are replaced by loopback signals.  
0 = Normal PCM receive  
1 = RSER and RMSYNC supplied by PCM transmit inputs  
HP_LOOP  
Loopback Towards HDSL on the PCM Side—The TSER and TMSYNC inputs are replaced by  
data and multiframe sync generated from the PCM receive formatter, without switching the  
PCM transmit clock. The MPU must change TCLK_SEL to source TCLK from the RCLK  
output. The PCM receiver operates normally, but the transmit TSER and TMSYNC inputs are  
ignored.  
0 = Normal PCM transmit operation  
1 = Transmit PCM data supplied by PCM receiver channel  
NOTE:  
PP_LOOP and HP_LOOP cannot be activated simultaneously.  
PCM_FLOAT  
Float PCM Multiframes—Selects whether MSYNC accepts TMSYNC as a frame and/or  
multiframe sync reference. MSYNC is always used to establish transmit frame and multiframe  
alignment for PCM and HDSL frames. If PCM_FLOAT is active, MSYNC ignores TMSYNC  
and allows unframed or asynchronous payload mapping of PCM frames into HDSL frames. In  
this case, TFRAME_LOC and TMF_LOC [addr 0xC0–0xC2] are also ignored. When  
PCM_FLOAT is zero, the TMSYNC input acts as the frame and/or multiframe sync reference  
for MSYNC.  
0 = MSYNC accepts TMSYNC as transmit sync reference  
1 = MSYNC ignores TMSYNC  
GCLK_SEL  
General Purpose Clock Source—Synchronizes MPU bus cycles and quantizes DPLL phase  
error.  
0 = GCLK supplied by HFCLK ÷ PLL_DIV  
1 = GCLK supplied by TCK pin  
N8953BDSB  
Conexant  
4-45