4.0 Registers
RS8953B/8953SPB
4.11 Common Command
HDSL Channel Unit
4.11 Common Command
Table 4-8. Common Command Write Registers
Address
Register Label
Bits
Name/Description
0xE5
0xE6
0xE7
0xE8
0xE9
0xF3
0xF4
CMD_1
CMD_2
CMD_3
CMD_4
CMD_5
CMD_6
CMD_7
8
8
8
8
8
8
7
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
Configuration
0xE5—Command Register 1 (CMD_1)
7
6
5
4
3
2
1
0
E1_MODE
PLL_DIS
PLL_DIV[1:0]
PLL_MUL[3:0]
PLL_MUL[3:0]
PLL Multiplication Factor—The MCLK input frequency is multiplied from 1 to 16 times by
the selected value to create an internal HFCLK approximately equal to 70 MHz and in the
range of 60 to 80 MHz for DPLL clock recovery. When PLL_MUL has a value of 0xF, the PLL
output is invalid.
PLL_MUL [hex]
MCLK Multiplier 16 15 14 13 12 11 10
0
1
2
3
4
5
6
7
9
8
8
9
7
A
6
B
5
C
4
D
3
E
2
F
–
PLL_DIV[1:0]
PLL Division Factor—Selects a divisor to scale down the internal HFCLK frequency to create
a General Purpose Clock (GCLK) in the frequency range of 10–15 MHz. PLL_DIV
determines the GCLK frequency for the DPLL phase detector and loop filter.
PLL_DIV
HFCLK Divisor
00
01
10
11
2
4
6
8
PLL_DIS
PLL Disable—Disables the internal PLL which normally generates HFCLK. When disabled, a
60 to 80 MHz HFCLK must be applied externally on the MCLK input.
0 = Normal PLL operation
1 = Disable PLL (PLL_MUL value has no effect)
E1_MODE
E1 or Nx64 Mode—Enables insertion of Z-bits from the TZBIT [addr 0x04] registers, and
extraction of Z-bits into the RZBIT [addr 0x04] registers. Otherwise, F-bits occupy the first bit
of HDSL payload blocks.
0 = HDSL payload includes F-bits (T1 mode)
1 = HDSL payload includes Z-bits (E1 mode)
4-44
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
