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RS8953SPBEPJ 参数 Datasheet PDF下载

RS8953SPBEPJ图片预览
型号: RS8953SPBEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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4.0 Registers  
RS8953B/8953SPB  
4.9 DPLL Configuration  
HDSL Channel Unit  
0xD6—DPLL Residual (DPLL_RESID_HI)  
7
6
5
4
3
2
1
0
DPLL_RESID[15:8]  
DPLL_RESID[15:0] DPLL Residual—Works in conjunction with DPLL_FACTOR to define the DPLL nominal  
free-running frequency in Open Loop Mode or the DPLL initial frequency in Closed Loop  
Mode [DPLL_NCO in CMD_5; addr 0xE9]. The DPLL_RESID value is sampled by the  
DPLL only after the MPU writes RX_RST [address 0xF1], or after the master HDSL channels  
receive framer transitions to an IN_SYNC state.  
DPLL_RESID = round(FRACTION × 65535)  
DPLL_FACTOR = 257 – INTEGER  
where: round ( )  
FRACTION = Fraction from INTEGER.FRACTION calculation  
INTEGER = Integer from INTEGER.FRACTION calculation  
= Round to nearest integer  
Assuming MCLK operates at eight times the BCLKn frequency (16 times symbol rate) and RCLK is desired  
to operate at standard T1 or E1 clock rates. The following examples show HTU application values for  
DPLL_RESID and DPLL_FACTOR:  
HTU  
2T1  
3E1  
2E1  
PLL_MUL  
PLL_DIV  
DPLL_FACTOR  
0xEB  
DPLL_RESID  
0x578B  
11  
11  
8
6
6
6
0xF1  
0xD7FF  
0xEF  
0x4000  
0xD7—DPLL Factor (DPLL_FACTOR)  
7
6
5
4
3
2
1
0
DPLL_FACTOR[7:0]  
DPLL_FACTOR[7:0] DPLL Factor—Works in conjunction with DPLL_RESID.  
4-36  
Conexant  
N8953BDSB