RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.9 DPLL Configuration
4.9 DPLL Configuration
Table 4-6. DPLL Configuration Write Registers
Address
Register Label
Bits
Name/Description
0xD5
0xD6
0xD7
0xD8
0xDB
0xF6
DPLL_RESID_LO
DPLL_RESID_HI
DPLL_FACTOR
DPLL_GAIN
8
8
DPLL Residual
DPLL Residual
DPLL Factor
DPLL Gain
8
7
DPLL_PINI
8
DPLL Phase Detector Init (optional for RS8953B)
DPLL Phase Detector Reset
DPLL_RST
—
The DPLL synthesizes the PCM Receive Clock (RCLK) output from the 60 through 80 MHz Reference Clock
(HFCLK) generated internally by PLL multiplication of MCLK, or input directly on MCLK [see PLL_MUL
and PLL_DIS in CMD_1; addr 0xE5]. HFCLK must operate in the 60 to 80 MHz frequency range, but requires
no specific phase or frequency relationship to the PCM or HDSL channels. The nominal frequency (f
) of
PCM
RCLK is synthesized by setting the DPLL_FACTOR and DPLL_RESID values according to the integer and
fractional results of the following formula:
f
× PLL_MUL
--M-----C---L---K------------------------------------
[INTEGER.FRACTION] =
2 × fPCM
where: f
= MCLK input frequency
MCLK
f
= RCLK output frequency desired
PCM
INTEGER
= Integer part of result [DPLL_FACTOR; addr 0xD7]
FRACTION = Fractional part of result [DPLL_RESID; addr 0xD5]
PLL_MUL
PLL_DIV
= PLL multiplication factor [CMD_1; addr 0xE5]
= PLL scale factor [CMD_1; addr 0xE5]
The DPLL phase detector operates from the 10–15 MHz General Purpose Clock (GCLK) which equals
HFCLK divided by PLL scale factor:
f
× PLL_MUL
--M-----C---L---K------------------------------------
GCLK =
PLL_DIV
0xD5—DPLL Residual (DPLL_RESID_LO)
7
6
5
4
3
2
1
0
DPLL_RESID[7:0]
N8953BDSB
Conexant
4-35
CONEXANT [ CONEXANT SYSTEMS, INC ]
