CX82100 Home Network Processor Data Sheet
Indirect/Table Linked List Descriptor Mode
The example shown in Figure 4-3 illustrates the use of the indirect/table linked descriptor
mode for four transmit buffers. The DMAC operation is virtually identical to that of the
embedded tail linked list descriptor mode except that the next DMA Ptr1 and Cnt1 will
be fetched from a pre-programmed pointer/counter table. The table itself is operated in a
circular fashion, meaning that the DMAC will automatically fetch the next
pointer/counter pair from the top of the table as soon as the last pointer/counter pair has
been used. The base address of the table is pre-stored in the DMAC_{x}_Ptr2 register.
The size of the table (in number of qwords) is pre-stored in the DMAC_{x}_Cnt2
register. Note that DMAC_{x}_Ptr1 and DMAC_{x}_Cnt1 registers should be initialized
to contain the Ptr1/Cnt1 values associated with the first buffer. The same Ptr1/Cnt1
values should also be stored at the bottom of the table in order to make the four buffers
work together like a big circular buffer.
Figure 4-3. Indirect/Table Linked List Descriptor Example 1
DMAC_{x}_Ptr1= 0x001400F8
DMAC_{x}_Cnt1 = 0x01000009
4 Bytes
Address
0x001400F8
0x001400FC
0x00140100
descriptor/status
0
8
64-byte
data packet #1
0x0014013C
0x00140140
DMAC_{x}_Ptr2= 0x00140800
DMAC_{x}_Cnt2 = 0x00000004
0x001402F8
0x001402FC
descriptor/status
0
8
Address
0x00140300
0x001402F8
0x01000009
0x001404F8
0x01000009
0x001406F8
0x01000009
0x001400F8
0x01000009
0x00140800
0x00140804
64-byte
data packet #2
0x0014033C
0x00140340
0x00140808
0x0014080C
0x00140810
0x00140814
0x001404F8
0x001404FC
0x00140500
descriptor/status
0
8
0x00140818
0x0014081C
64-byte
data packet #3
0x0014053C
0x00140540
0x001406F8
0x001406FC
descriptor/status
0
8
0x00140700
64-byte
data packet #4
0x0014073C
0x00140740
101545_012
4-12
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