CX82100 Home Network Processor Data Sheet
4
DMAC Interface Description
The DMA controller (DMAC) is both an ASB master and an APB master. It is integrated
with the ASB-to-APB bridge. Using burst transfers and pipelining the data within the bus
bridge interface optimizes ASB efficiency.
The DMAC always performs qword (8 bytes) data transfers which require data valid on
the entire 64-bit APB data bus. Burst transfer on APB is not supported, however, data can
be transferred on consecutive APB cycles (PCLK cycles) for either read or write.
4.1
DMA Channel Definition
The DMAC supports the data stream channels defined in Table 4-1. Each channel’s data-
flow is considered with respect to the system memory’s point-of-view. A source channel
has the memory supplying data to the DMAC and on to the transmitter's output port. A
destination channel is one where the memory receives data through the DMAC from the
receiver's input port.
Table 4-1. DMA Channel Definition for DMAC
DMA Channel No.
Channel Type
Src/Dst
Channel Description
EMAC1-TxD
EMAC1-RxD
EMAC2-TxD
EMAC2-RxD
Reserved
Reserved
M2M In
M2M Out
USB-TxD_EP3
USB-TxD_EP2
USB-TxD_EP1
USB-RxD
DMA Mode
Lnk Lst – restart
Circ Bfr – restart
Lnk Lst – restart
Circ Bfr – restart
1
2
3
4
5
6
7
8
9
10
11
12
13
Dst
Src/Dst
Dst
Src
Dst
Src
Dst
Src
Src
Src
Dst
Src
Src
Dst
Lnk Lst
Lnk Lst
Lnk Lst
Circ Bfr – restart
Lnk Lst
USB-TxD_EP0
4.2
DMA Requests and Data Transfer
The APB peripherals issue DMA data transfer requests to the DMAC. The knowledge of
how much data will be received or transmitted resides within the peripheral. The physical
interface transfers can be controlled to bit transfer resolution even though the DMAC
only operates at qword resolution. So the size of the packets actually DMAed (which may
differ from that transmitted or received) is under peripheral control. The DMAC just
generates sequential incrementing addresses. Table 4-2 lists all the request commands
supported by DMAC.
DMA action requests are signaled by encoding X{x}R where {x} represents the channel
number. The signal X{x}R should remain idle except when issuing a specific request to
the DMAC. Each event is signaled during a single PCLK clock cycle. It is acceptable to
have an interrupt or abort event directly follow a data transfer request. When an APB data
101306C
Conexant Proprietary and Confidential Information
4-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
