CX82100 Home Network Processor Data Sheet
Figure 3-3. Boot Procedure
Internal ROM boot(GPIO14=1)
GPIO14 boot option pin
Flash boot(GPIO14=0)
Power-On-Reset
Power-On-Reset
Begin execution of the
ROM code.
Begin execution of Flash
mapped to ROM address
space.
Read signature
bytes (first 4
bytes) of
Flash boot code
copies itself into
SRAM.
EEPROM.
Set Run-Map bit to
swap ROM and RAM
address space. Now
executing out of
SRAM.
Is the signature
present?
N
Y
Read from EEPROM,
Device Descriptor, Device
Config., endpoint config.,
Lang. string ID, Manuf.
string ID, Prod. string ID,
and store in SRAM.
Read from internal ROM,
Device Descriptor, Device
Config., endpoint config.,
Lang. string ID, Manuf.
string ID, Prod. string ID,
and store in SRAM.
Enable SDRAM.
Set up
FCLK and BLCK
frequencies.
Load UDC, EPINFO,
ENDPTBUFs,
CONFIGBUFs,
STRINGBUFs, with
SRAM data.
Copy application
firmware from
flash to SDRAM.
Jump to start of
application firmware
in SDRAM and
execute.
Continuous loop
waiting for USB
traffic.
Typical Flash
boot scenario.
101545_009
101306C
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