CX82100 Home Network Processor Data Sheet
peripheral makes a DMA data transfer request, however, it should not make another until
after the current request has been processed (APB read or write). It is left up to the
requestor (not the DMAC) to log any overflow or underflow conditions.
Table 4-2. DMA Requests for APB Peripherals
X{x}R
3’b000
3’b001
3’b010
3’b011
3’b100
Request
DMA_IDLE
DMA_INTR
DMA_SAVE
DMA_RELD
DMA_XNXT
DMAC Action
None
Data Pkt Done interrupt forwarded to interrupt controller.
Save channel’s state (cnt and/or ptr).
Reload or restore channel’s state from previous save.
Data transfer request @ current pointer. Ptr1+ = 8 (1 qword),
Cnt1-- (Cnt1 represents the number of qwords)
3’b101
3’b110
3’b111
DMA_XSAV
DMA_XNUL
Data transfer request @ saved pointer. Ptr2+ = 8 (1 qword),
Cnt2-- (Cnt2 represents the number of qwords)
Advance current pointer, skip data transfer. Ptr1+ = 8
(1 qword), Cnt1-- (Cnt1 represents the number of qwords)
Reserved
Note that DMA_XNXT and DMA_XSAV are the only DMA commands that cause a
data transfer. Once issued, the channel requestor should not issue another until after their
APB DMA port has been accessed. The APB DMA port qword read or write serves as
the DMAC acknowledge to the channel requestor.
The actions DMA_SAVE, DMA_RELD, and DMA_XNUL should not be issued during
a pending data transfer request since the current pointer and counter are not updated until
the channel is serviced. Usually DMA_SAVE will be issued just after the packet’s last
qword transfer acknowledge. Usually DMA_RELD is issued when a channel decides to
abort a packet. DMA_XNUL is typically issued before starting a packet transfer.
The action DMA_XNUL can be issued on consecutive PCLKs if the channel desires to
move up its current pointer by several qwords. This action may not be issued when the
DMAC_{x}_Cnt1 is equal to 1. DMA_XNUL may not be used just before an address
link. Normally, when DMA_XNXT is issued for the last data qword, both the link and
data transfers are scheduled concurrently, with the link transfer actually occurring first.
Two problems arise if DMA_XNUL is allowed to decrement the qword counter quickly.
First, the address is changed before a link transfer can be scheduled into the DMAC
transfer queue with the correct address. Second, there is nothing to prevent the requesting
channel from issuing a DMA_XNXT before the new address link is updated.
4.3
Control Registers
Per each DMA channel {x}, the DMAC can support three basic modes of address
generation using up to two 22-bit dword- (4 bytes) aligned address pointers
(DMAC_{x}_Ptr1, DMAC_{x}_Ptr2) and/or up to three 11-bit qword (8 bytes) counters
(DMAC_{x}_Cnt1, DMAC_{x}_Cnt2, DMAC_{x}_Cnt3). DMAC_{x}_Ptr1 will
always be readable as the current qword pointer. The counters are large enough to allow a
maximum DMA contiguous block transfer of 16 KB (less 1 qword). Each channel {x} is
handled uniquely and specifically for operating mode, priority, and data rate. Recall that
the peripheral is in control of initiating, aborting, and ending the DMA transfer requests.
Pointers are 22-bit programmable and dword-aligned. The pointer registers are bit-
aligned to represent the pointers as 24-bit byte-addresses. Thus the pointer registers
should be written and read as 24-bit byte-addresses. However, the lower two bits are
fixed at 2’b00 forcing the pointers to be dword-aligned. Recall that data transfer
resolution is limited to whole qwords.
4-2
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