CX82100 Home Network Processor Data Sheet
4.5
Control Register Formats
4.5.1
DMAC x Current Pointer 1 (DMAC_{x}_Ptr1)
Bit(s)
31:24
23:2
Type
Default
22’bx
Name
Description
Reserved.
RW*
DMAC_{x}_Ptr1
Current DMA qword Address Pointer.
Points to next qword transfer location within source or destination
buffer. Always dword-aligned.
1:0
Reserved.
4.5.2
DMAC x Indirect/Return Pointer 1 (DMAC_{x}_Ptr2)
Bit(s)
31:24
23:2
Type
Default
22’bx
Name
Description
Reserved.
RW*
DMAC_{x}_Ptr2
Indirect or Return DMA qword Address Pointer.
Points to next pointer which points to next qword transfer location
within source or destination buffer. Always dword-aligned.
1:0
Reserved.
4.5.3
DMAC x Buffer Size Counter 1 (DMAC_{x}_Cnt1)
Bit(s)
31:26
25:24
Type
Default
2’b00
Name
Description
Reserved.
DMA Linked List Mode.
00 = ptr/cnt at buffer tail.
RW
DMAC_{x}_LMode
01 = ptr/cnt at Ptr2 (table).
10 = ptr/cnt at Ptr2 (return ptr).
11 = Reserved.
23:11
10:0
Reserved.
RW*
11’bx
DMAC_{x}_Cnt1
Initialize to DMA Buffer Size in No. of qwords.
Decrements during DMA data transfers and reloads at end of buffer.
Note that a write to DMAC_{x}_Cnt1 also loads buffer size to
DMAC_{x}_Cnt2.
4.5.4
DMAC x Buffer Size Counter 2 (DMAC_{x}_Cnt2)
Bit(s)
31:11
10:0
Type
Default
Name
Description
Reserved.
Saved DMA Buffer Size in No. of qwords.
RW*
11’bx
DMAC_{x}_Cnt2
4-4
Conexant Proprietary and Confidential Information
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