CX82100 Home Network Processor Data Sheet
3.3
Endianness
The internal bus architecture supports only Little-Endian mode addressing (see Figure
3-2). Support for Big-Endian mode may occur in a peripheral that handles its data stream
or in the host interface which may exchange data with a Big-Endian mode external
processor.
Figure 3-2. Little-Endian Mode Addressing
BA[1:0]=3
BA[1:0]=2
BA[1:0]=1
BA[1:0]=0
31:24
23:16
15:8
7:0
Data Bus
Byte Lane No.
3
2
1
0
100878-008
3.4
Boot Procedure
There are two different scenarios for the boot procedure depending on the state of the
BOPT (GPIO14) pin. Upon power-on or reset, boot code will execute from internal ROM
if the BOPT (GPIO14) pin is high or from external Flash ROM if the BOPT (GPIO14)
pin is low.
When booting from internal ROM, the boot code reads EEPROM information (if an
EEPROM is installed) to set up the USB configuration of the HNP. Once complete, USB
communication between PC and the HNP can occur.
When booting from external Flash ROM, the HNP maps the first MB of external Flash
ROM space to internal ROM space (see memory map in Figure 3-1 for detailed
information). A typical boot procedure begins by copying the flash boot code to internal
RAM. The RUN_MAP bit is set in the Host Control Register (see 5.3.1) which causes the
boot code to begin execution from internal RAM. The boot code then configures the
clocks and the enables the SDRAM. This enables the boot code to begin execution from
internal RAM. The boot code then copies the application firmware residing in flash to
SDRAM. The boot code then jumps to the start of the application firmware in SDRAM.
Figure 3-3 illustrates the boot procedure.
3-4
Conexant Proprietary and Confidential Information
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