CX82100 Home Network Processor Data Sheet
3.2
Starting Addresses
The starting addresses for mapping ASB and APB slaves are defined in Table 3-1 and
Table 3-2, respectively.
Table 3-1. Starting Addresses for Mapping ASB Slaves
ASB Address:
ASB Slave
Description
BA[31:0]
0x000XXXXX
0x0018XXXX
External Flash
ROM/Internal RAM
16k x 32 Internal ROM/External Flash ROM
(Boot-Time);
8k x 32 Internal RAM (Run-Time)
Internal RAM/Internal ROM 8k x 32 Internal RAM (Boot-Time);
16k x 32 Internal ROM (Run-Time)
0x002XXXXX
0x003XXXXX
Host Interface
ASB-to-APB Bridge/DMAC
Host Master Mode peripherals interface
To ASB-to-APB Bridge and APB peripherals
– dword (4 bytes) access only
0x00400000–
0x007FFFFF
External Flash ROM
External SDRAM
ARM940T
Host Master Mode interface to 4 MB Flash
0x00800000 -
External SDRAM/SRAM interface to 8 MB
SDRAM or up to 1 MB SRAM
ARM940T TIC Access
0x00FFFFFF
0x80000000
Table 3-2. Starting Addresses for Mapping APB Slaves
ASB Address:
APB Slave
Description
BA[31:0]
0x0030XXXX
0x0031XXXX
0x0032XXXX
0x0033XXXX
0x0034XXXX
0x0035XXXX
ASB-to-APB Bridge/DMAC
EMAC 1
EMAC 2
USB Interface
Reserved
ASB-to-APB Bridge Slave and DMAC
Ethernet Media Access Control 1
Ethernet Media Access Control 2
USB Device Controller
Interrupts, Timers, GPIO,
Miscellaneous Peripherals (Interrupts, Timers,
GPIOs, and Clock)
Clock (ITGC)
3.2.1
ARM Vector Table
Table 3-3 shows the exception vector addresses required by the ARM940T. The first 32-
byte space of the ASB address space is reserved for this table.
Table 3-3. ARM Exception Vector Addresses
Address
Exception
Mode on Entry
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
0x0000001C
Reset
Supervisor
Undefined
Supervisor
Abort
Abort
Reserved
IRQ#
Undefined Instruction
Software Interrupt
Abort (Prefetch)
Abort (Data)
Reserved
IRQ#
FIQ#
FIQ#
101306C
Conexant Proprietary and Confidential Information
3-3
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