CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.3 System Bus
Figure 2-13. T1 Line to E1 System Bus Time Slot Mapping
Frame A
Frame B
3 4
FA
1
2
3
4
5
6
22 23 24 FB
1
2
RNRZ
u
u
7
u
u
RPCMO
27
0
1
2
3
4
5
6
28 29 30 31
0
1
2
NOTE(S):
(1)
u = unassigned time slots
FA = T1 frame bit, frame A
FB = T1 frame bit, frame B
(2)
(3)
RSLIP has four modes of operation: Two Frame Normal, 64-bit Elastic,
Two-Frame Short, and Bypass. RSLIP mode is set in the Receive System Bus
Configuration register [RSB_CR; addr 0D1]. RSLIP is organized as a two-frame
buffer. This allows MPU access to frame data, regardless of the RSLIP mode
selected. Each byte offset into the frame buffer is a different time slot: offset 0 in
RSLIP is always time slot 0 (TS0), offset 1 is always TS1, and so on. The slip
buffer has processor read/write access.
Two-Frame Normal
In Normal mode, the slip buffer total depth is two 193-bit frames (T1) or two
256-bit frames (E1). Data is written to the slip buffer using RXCLK, and read
from the slip buffer using RSBCK. If a slight rate difference between the clocks
occurs, the slip buffer changes from its initial condition—approximately half
full—by either adding or removing frames. If RXCLK writes to the slip buffer
faster than RSBCK reads the data, the buffer will fill up. When the slip buffer in
Normal mode is full, an entire frame of data is deleted. Conversely, if RSBCK
reads the slip buffer faster than RXCLK writes the data, the buffer will become
empty. When the slip buffer in Normal mode is empty, an entire frame of data is
duplicated. When an entire frame is deleted or duplicated it is known as a Frame
Slip (FSLIP), which is always one full frame of data. The FSLIP status is reported
in the Slip Buffer Status register [SSTAT; addr 0D9]. In T1 mode, the F-bit is
treated as part of the frame and can slip accordingly.
100054E
Conexant
2-29
CONEXANT [ CONEXANT SYSTEMS, INC ]
