CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.3 System Bus
The RSB maps line rate time slots to system bus time slots. The 24 (DS1) or
32 (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus
time slots as listed in Table 2-4. The system bus rate must be greater than or equal
to the line rate, except for 1536K bus mode.
Table 2-4. RSB Interface Time Slot Mapping
Source
Channels
System Bus Rate
(MHz)
Destination Time
Slots
Line Rate (MHz)
1.544
24
24
24
24
24
32
32
32
1.536
1.544
2.048
4.096
8.192
2.048
4.096
8.192
24
24
32
64
128
32
2.048
64
128
The RSB, Figure 2-12, consists of a timebase, slip buffer, a signaling buffer,
and a signaling stack.
Figure 2-12. RSB Diagram
RSIG
STACK
RSIG
Buffer
RSIGO
RPCMO
SIGFRZ
RSIG
Local
RSLIP
Buffer
RNRZ
AIS
RINDO
RFSYNC
RMSYNC
RSB
From
Receive
Timebase
RPHASE
Timebase
RSBCK
RSBCKI
TSBCKI
I/O From Pins
}
Remote
Local
Channel
Channel
Loopback
Loopback
100054E
Conexant
2-27
CONEXANT [ CONEXANT SYSTEMS, INC ]
