CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.3 System Bus
Figure 2-9 illustrates the relationship between these signals. Signal definitions
are provided in Table 1-6, Hardware Signal Definitions. RSB data outputs can be
configured to output on the rising or falling edge of RSBCKI (see the Receive
System Bus Configuration register [RSB_CR; addr 0D1]).
Figure 2-9. RSB Waveforms
RSBCKI
Frame 48 TS 31
Frame 1 TS 0
RPCMO
RINDO
RSIGO
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
A
1
B
C
D
A
5
B
6
C
7
D
8
A
F
B
1
C
D
A
4
B
5
C
6
D
7
A
8
B
1
Frame 48 TS 24
Frame 1 TS 1
RPCMO
RINDO
2
3
4
2
3
A
B
C
D
A
B
C
D
X
A
B
C
D
A
B
C
D
A
RSIGO
SIGFRZ
RFSYNC
RMSYNC
NOTE(S): The Receive Multiframe Sync (RMSYNC) occurs every 6 ms, 48 T1 or 48 E1 frames.
The RSB supports five different system bus rates (MHz):
•
•
•
•
•
1.536 MHz—T1 rate, 24 time slots, without framing bit
1.544 MHz—T1 rate with framing bit
2.048 MHz—E1 rate, 32 time slots
4.096 MHz—twice the E1 rate, 64 time slots
8.192 MHz—four times the E1 rate, 128 time slots
100054E
Conexant
2-25
CONEXANT [ CONEXANT SYSTEMS, INC ]
