2.0 Circuit Description
CX28394/28395/28398
2.3 System Bus
Quad/x16/Octal—T1/E1/J1 Framers
The 4.096 and 8.192 MHz bus modes contain multiple bus members (A, B,
C, D) which allow multiple T1/E1 signals to share the same system bus. This is
done by interleaving the time slots from up to four framers, without external
circuitry (see Figures 2-10 and 2-11). The system bus rate is independent of the
line rate and must be selected using the System Bus Interface Configuration
register [SBI_CR; addr 0D0].
Figure 2-10. RSB 4096K Bus Mode Time Slot Interleaving
RSBCKI
RPCMO
TS31A
TS31B
TS0A
TS0B
RSIGO
SIG31A
SIG31B
SIG0A
SIG0B
RFSYNC
NOTE(S): A and B time slot comes from different framers. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1].
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate.
Figure 2-11. RSB 8192K Bus Mode Time Slot Interleaving
RSBCKI
RPCMO
RSIGO
TS31A
TS31B
TS31C
TS31D
TS0A
TS0B
TS0C
TS0D
SIG31A
SIG31B
SIG31C
SIG31D
SIG0A
SIG0B
SIG0C
SIG0D
RFSYNC
NOTE(S): A, B, C, and D data comes from different framers. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1].
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate. RSB.OFFSET equals
zero.
2-26
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
