2.0 Circuit Description
CX28394/28395/28398
2.3 System Bus
Quad/x16/Octal—T1/E1/J1 Framers
2.3.5 Transmit System Bus
The Transmit System Bus (TSB) consists of a timebase, slip buffer, signaling
buffer, and transmit framer (Figure 2-15). It provides a high-speed serial interface
between the XMTR and the system bus.
Figure 2-15. TSB Interface Block Diagram
RSBCKI
TSBCKI
TINDO
TFSYNC
TMSYNC
From
Transmit
Timebase
TSB
Timebase
TPHASE
Transmit
Framer
TXDATA
TPCMI
TSIGI
TSLIP
Buffer
TNRZ
TSIG
Local
TSIG
Local
The TSB contains the following five pins:
Pin Name
Function
TSBCKI
TPCMI
Transmit System Bus Clock
Transmit PCM Data
TFSYNC/TMSYNC
Transmit Frame Sync or
Transmit Multiframe Sync
Transmit Time Slot Indicator or
Transmit Datalink Clock
Transmit Signaling Data or
Transmit Datalink Data
TINDO/TDLCKO
TSIGI/TDLI
2-32
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
