CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.3 System Bus
Refer to Figure 2-16 for the relationship between these signals. Signal
definitions are provided in Table 1-6, Hardware Signal Definitions. TSB data
outputs can be configured to input data on the rising or falling edge of TSBCKI
(see the Transmit System Bus Configuration register [TSB_CR; addr 0D4].
Figure 2-16. Transmit System Bus Waveforms
TSBCKI
Frame 48 TS 31
Frame 1TS 0
TPCMO
TINDO
TSIGI
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
X
1
X
X
X
A
5
B
6
C
7
D
8
X
F
X
1
X
X
A
4
B
5
C
6
D
7
X
8
X
1
Frame 48 TS 24
Frame 0 TS 1
TPCMI
TINDO
2
3
4
2
3
X
X
X
X
A
B
C
D
X
X
X
X
X
A
B
C
D
X
TSIGI
TFSYNC
TMSYNC
The TSB supports five different system bus rates (MHz):
•
•
•
•
•
1.536 MHz—T1 rate, 24 time slots, without framing bits
1.544 MHz—T1 rate with framing bits
2.048 MHz—E1 rate, 32 time slots
4.096 MHz—twice the E1 rate, 64 time slots
8.192 MHz—four times the E1 rate, 128 time slots.
100054E
Conexant
2-33
CONEXANT [ CONEXANT SYSTEMS, INC ]
