3.0 Registers
CX28394/28395/28398
3.16 System Bus Registers
Quad/x16/Octal—T1/E1/J1 Framers
120–13F—Transmit Signaling Buffer (TSIGn; n = 0 to 31)
Transmit signaling from the TSIGI pin is automatically placed into the TSIGn buffer. Processor controls TSIGn
insertion into the transmitter output by selecting TSIGO[inTPCn]. The processor can read monitor TSIGn from
system supplied signaling or can use TSIGn for inter-processor communication. During E1 modes, TSIG0 and
TSIG16 buffer locations hold the CAS multiframe alignment signal (MAS.1 through MAS.4), Extra bits (X.1
through X.4), and multiframe yellow alarm (MYEL) bits supplied from TSIGI.
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
—
—
TSIGn[3]
TSIGn[2]
TSIGn[1]
TSIGn[0]
TSIG0 (E1)
TSIG16 (E1)
TSIGn.3.
Input Signaling A Bit
Input Signaling B Bit
Input Signaling C Bit
Input Signaling D Bit
MAS.1
MAS.2
MAS.3
MAS.4
X.1
TSIGn.2.
TSIGn.1.
TSIGn.0.
MYEL
X.3
X.4
140–15F—Transmit PCM Slip Buffer (TSLIP_LOn; n = 0 to 31)
7
6
5
4
3
2
1
0
TPCM[1]
TPCM[2]
TPCM[3]
TPCM[4]
TPCM[5]
TPCM[6]
TPCM[7]
TPCM[8]
TPCM[1]
First bit
TPCM[2]
TPCM[3]
TPCM[4]
TPCM[5]
TPCM[6]
TPCM[7]
TPCM[8]
Second bit
Third bit
Fourth bit
Fifth bit
Sixth bit
Seventh bit
Eighth bit received on TPCMI
3-112
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
