3.0 Registers
CX28394/28395/28398
3.16 System Bus Registers
Quad/x16/Octal—T1/E1/J1 Framers
AB Signaling (Per-Channel RSIG_AB [with DEBOUNCE])—Debounce is applicable only
for T1 modes and affects the RSIGn input buffer update mechanism. This is accomplished by
comparing, on a bit-by-bit basis, the present received input signaling bit value with the current
buffered signaling bit values from two prior multiframes. If signaling from prior multiframe
(N) differs from input, and input equals buffered value from 2 multiframes prior (N-1),
signaling bit value from multiframe N is inverted when the input buffer is updated.
Sig Input
Buffer N, N-1
Update N, N-1
Notes
—
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
00
00
00
01
10
11
11
11
Change update
Debounce
—
—
Debounce
Change update
—
When RIDLE is active in an unassigned time slot defined to carry embedded F-bits,
EMFBIT replaces all embedded F-bit outputs on RPCMO with the programmed value.
0 = normal ABCD and embedded F-bit throughput
1 = AB signaling and embedded F-bit replacement
RIDLE
Time Slot Idle—When RIDLE is active, the incoming RX time slot data is only updated in the
RSLIP_HIn buffer, and the RSB time slot data output is only extracted from RSLIP_LOn
buffer. Thus, the processor can write an 8-bit idle code pattern in RSLIP_LOn buffer for
output during the RSB time slot.
0 = no effect
1 = RSB time slot replaced by contents of RSLIP_LOn
SIG_STK
Receive Signaling Stack—Selects whether changes detected in the ABCD signaling value are
reported in signaling stack [addr 0DA]. Note that signaling for all time slots is continuously
updated in RSIGn buffer, regardless of the SIG_STK setting.
0 = no effect
1 = signaling stack
RLOCAL
Enable Local Signaling Output—Determines whether the RSIGO output signaling and
RPCMO inserted signaling [INSERT; addr 0E0-0FF] are supplied from RSIGn output buffer
or processor supplied local signaling from RSIGA–RSIGD.
0 = RSIGn buffer signaling
1 = RSIGA-RSIGD local signaling
RSIGA–RSIGD
Local Receive Signaling—When RLOCAL is active, these 4 bits are inserted into RSIGO
instead of the buffered signaling from RSIGn. If both RLOCAL and INSERT are active, these
4 bits are also inserted into RPCMO during system bus signaling frames.
0 = output signaling bit equals zero
1 = output signaling bit equals one
3-114
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
