CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.16 System Bus Registers
1A0–1BF—Receive Signaling Buffer (RSIGn; n = 0 to 31)
The Receive Signaling Buffer (RSIGn) contains all ABCD signaling inputs from all channels, regardless of
whether signaling is active [SIG_STK; addr 180–19F]. RSIGn is not updated during signaling freeze
conditions, or when the receive framer is configured in a non-signaling mode. Normal signaling buffer
operation transfers ABCD input to ABCD output coincident with the D-bit update (in T1 mode) or coincident
with receipt of respective channel's ABCD signaling during TS16 (in E1 mode). When DEBOUNCE is active,
output signaling for active channels is updated coincident with the sampling of each input signaling bit and may
cause the buffered output value to transition in the middle of the received multiframe.
7
6
5
4
3
2
1
0
RSIGn[7]
RSIGn[6]
RSIGn[5]
RSIGn[4]
RSIGn[3]
RSIGn[2]
RSIGn[1]
RSIGn[0]
RSIGn[7]
Output Signaling A Bit
Output Signaling B Bit
Output Signaling C Bit
Output Signaling D Bit
RSIGn[6]
RSIGn[5]
RSIGn[4]
RSIG16 (E1)
RSIG0 (E1)
MAS.1
RSIGn[3].
RSIGn[2].
RSIGn[1].
RSIGn[0].
Input Signaling A Bit
Input Signaling B Bit
Input Signaling C Bit
Input Signaling D Bit
X.1
MAS.2
MYEL
X.3
MAS.3
MAS.4
X.4
1C0–1DF—Receive PCM Slip Buffer (RSLIP_LOn; n = 0 to 31)
7
6
5
4
3
2
1
0
RPCM[1]
RPCM[2]
RPCM[3]
RPCM[4]
RPCM[5]
RPCM[6]
RPCM[7]
RPCM[8]
RPCM[1]
First bit
RPCM[2]
RPCM[3]
RPCM[4]
RPCM[5]
RPCM[6]
RPCM[7]
RPCM[8]
Second bit
Third bit
Fourth bit
Fifth bit
Sixth bit
Seventh bit
Eighth bit received from receiver
100054E
Conexant
3-115